1. Field of the invention
The present invention relates to a method of forming a capacitor in a semiconductor device. More particularly, the present invention relates to a method of forming a capacitor in a semiconductor device capable of preventing contact plug damage and interlayer insulating film loss aligned below a storage electrode due to penetration of etchant when a TiN layer or a Ru layer is used as a storage electrode material.
2. Description of the Prior Art
Due to the rapid advancement of the semiconductor technologies, the semiconductor memories recently produced are more likely to be highly integrated to reduce the unit cell area and to lower the operational voltage of the semiconductor devices. However, even when the cell area is reduced, a sufficient capacitance above 25 fF/cell is required for a memory device in order to prevent the refresh time from being shortened without soft error.
Under the above circumstance, an SIS (silicon-insulator-silicon) capacitor employing a dielectric layer made from Al2O3 presents limitations for ensuring the capacitance required for next-generation DRAMs above 512M. For this reason, an MIS (metal-insulator-silicon) capacitor employing a TiN electrode and a dielectric layer made from HfO2/Al2O3 has been extensively developed.
In such an MIS capacitor, Tox (equivalent oxide thickness) may be limited to 12 Å. For this reason, if a metal wiring less than 70 nm is applied to the DRAMs, an effective area of a storage electrode may not exceed 0.85 μm2/cell even if a concave type storage electrode is employed, so that it is difficult to obtain the cell capacitance above 25 fF/cell.
Therefore, if a fine wiring less than 70 nm is applied to the DRAMs, it is essentially necessary to replace the concave type storage electrode with a cylinder type storage electrode to enlarge the effective area of the storage electrode for achieving the cell capacitance above 25 fF/cell. In addition, a cylinder type TIT (TiN-insulator-TiN) or RiT (Ru-insulator-TiN) capacitor employing a dielectric layer having a dielectric constant higher than that of currently used HfO2/Al2O3 or HfO2/Al2O3/HfO2 is necessary in order to obtain higher capacitance for the DRAMs.
However, if the cylinder type capacitor is fabricated by using the TiN layer or the Ru layer as a storage electrode material, following problems may occur.
In general, when the cylinder type capacitor is fabricated, a cylinder type storage electrode is first formed and then a wet etching process is carried out by using wet-etch chemical, such as diluted HF solution or BOE (NHF4+HF) solution, in order to remove a mold insulating layer.
However, as shown in FIG. 1, if the TiN layer or the Ru layer is used as the storage electrode material, the wet-etch chemical may penetrate into an interlayer insulating film 11 during the wet etching process through a path A formed in the storage electrode 15 and a path B formed at an interfacial surface between the storage electrode 15 and an etching barrier layer 14 made from a silicon nitride layer so that a polysilicon contact plug 12 and the interlayer insulating film 11 aligned below the storage electrode 15 may be damaged. Reference numeral 13 represents a diffusion barrier layer made from TiSi2.
FIG. 2 is a TEM photograph representing a diffusion barrier layer made from TiSi2, a polysilicon contact plug and an interlayer insulating film which are damaged by wet-etch chemical when the wet etching process is performed for removing a mold insulating layer.
Such a defect leads to an electric connection error causing malfunction of DRAMs and reduces a yield rate of semiconductor devices because the defect may occur over the whole area of a wafer, so that it is necessary to remove the defect.